As we showed in the previous post, a parallel to serial converter takes one clock cycle to load the shift register and provide a serial output. Such a scenario can be used for simulator. In other words, we can simulate various parallel to serial converter using the bottom right of Figure1. If we simulate the parallel to serial converter of this post, we will get three outputs when simulating it. The output should be simulated N times for N clock cycle (see Figure8 and the waveforms that are reported in Figure9, Figure10 and Figure11. if you compare the simulated waveforms with the fir line waveforms reported below). These waveforms are in simulation because we use manual sampling of waveforms in simulation. The parallel input clock of the serial to parallel converter is the same clock that is provided by the simulation. The float output is a proprietary signal in order to enforce perfect alignment and avoid waveshape glitches. In other words, the output waveform should be a sawtooth trace. The input data is the sequence of bits we are using for testing the code. We can choose any bit sequence, for instance, the bit sequence used by the Xilinx XC6Z200DFFG086 for the example in this post.
(see Figure2), the receiver terminal data is a flip flop. The D input is connected to the serialIn data line. The S and R on of the flip flop are configured with a pull up and a pull down respectively. The clock is the input clock and the Q of the flip flop is used to clock the shift register. When the S/R 1 is sampled, the R will be high and the data is shifted to the output. Then the S will be sampled as high as, and the data will shift until it will reach the R/Q out. The output of the r/q flip flop will be high as result of this, this is respected by the internal flip flop of the transmitter. When the data is shifted, the data has to be inverted. 7211a4ac4a